A Synthesizable RTL Design of Asynchronous FIFO Interfaced with SRAM
نویسندگان
چکیده
This paper demonstrates an asynchronous implementation of a FIFO based on 4 phase bundled data protocol, interfaced with an SRAM. Both FIFO and SRAM are modeled using VHDL and use the asynchronous handshaking principles for communication. Timing and power analysis for the design is also presented. The synthesis, simulation and analysis is done with the help of Xilinx ISE version 9.1i Keywords— asynchronous, FIFO, SRAM, interfacing, VHDL, delays, power
منابع مشابه
Asynchronous FIFO Design with Gray code Pointer for High Speed AMBA AHB Compliant Memory controller
An improved technique for FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains and asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. This method requires additional techniques to correctly synthesize and analyze the design, which are de...
متن کاملSynthesizing Asynchronous Micropipelines with Design Compiler
We present an asynchronous micropipeline synthesis flow supporting conventional synthesizable HDL specifications. Using Synopsys Design Compiler as the front-end interfacing behavior specification, the synthesis core and the final netlist front-end ensures easy integration into conventional design flow. With our RTL to micropipeline re-implementation engine in the backend, conventional HDL spec...
متن کاملNehalem Processor Core Made FPGA Synthesizable
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-of-the-art x86 design with the out-oforder micro-architecture is made FPGA synthesizable and capable of high-speed cycle-accurate emulation. Unlik...
متن کاملA Novel FIFO Design for Data Transfer in Mixed Timing Systems
In the current scenario, with the increasing integration densities, most system-on-chip designs are partitioned into multiple clock domains. In this paper, an asynchronous FIFO (First-in Firstout pipeline) design is employed as a data transfer interface between two independent clock domains. Since the clocks on the either sides of the FIFO run at a different speed, the task to ensure the correc...
متن کاملAsynchronous FIFO Interfaces for GALS On-Chip Switched Networks
In this paper we present a novel design approach that combines the advantages of on-chip switched networks (OCSNs) and the globally asynchronous, locally synchronous (GALS) design methodology using the mechanism of asynchronous FIFO buffers. Our proposed two GALS OCSN models were synthesized with 0.25μm Chip Express structured ASIC library. Comparative simulations were performed for these two p...
متن کامل